Frequency synthesizer having a phase-locked loop structure for fast generation of radio-frequency channels

ABSTRACT

Based on a phase lock loop structure, having a reference signal generator (1), a first phase detector (2), a low pass filter (3), a VCO (4) and a frequency divider (5), in order to achieve a faster channel switching an maintain the design of the filters to be as simple as possible, a second phase detector (6) is provided that receives the reference signal (9) and a second output signal (11) coming from the frequency divider (5) and shifted 90° with respect to its other output signal (10), and that generates a second phase error signal (13), in quadrature with the first phase error signal (12), that is filtered by a second low pass filter (7) thereby generating a second filtered phase error signal (15). The two filtered phase error signals (14,15) are provided to a quadratic correlator (8) whose output is provided to the VCO (4). Its amplitude is proportional to the difference of frequencies between the reference signal (9) and any of the output signals (10,11) from the frequency divider (5).

TECHNICAL FIELD

The present invention relates to communications and, more particularly,to a frequency synthesizer.

BACKGROUND TO THE INVENTION

There are many digital communication systems that make use ofMulti-Frequency Time Division Multiple Access techniques (MF-TDMA).These systems use frequency syntesizers for generating the channelfrequencies that will be used to transmit the digital information.

As the present systems work at high rates, it becomes necessary toreduce the guard time between consecutive time slots in order to keep ahigh efficiency of the system, which means that in case of a change inthe radio-frequency channel, the frequency synthesizer must switch itsold frequency to the new one quickly, as it is necessary to make surethat the new frequency is already established when the next time slot ofthe MF-TDMA system starts.

There are many techniques for minimizing the switching time betweenchannels.

Some of them are based on the use of a loop filter whose bandwidthvaries, being larger at the beginning when the loop is totally unlocked,and getting narrower when the loop is getting locked, as indicated inthe article "Phase loop design for TDMA Applications" by C. Ryan,published into the 1985 IEEE Military Communications ConferenceMILCOM'85, Vol. 2, pp. 320 to 323.

The main drawback of this type of techniques is that when it isnecessary to reduce the switching time between channels, it is alsonecessary to increase the complexity of the loop filter which results inthe synthesizer becoming more expensive and less reliable, increasingthe possibility that the frequency synthesizer stability may benegatively affected.

DISCLOSURE OF INVENTION

An object of the present invention is to reduce the switching timebetween channels, without increasing the complexity of the filter orfilters of the frequency synthesizer and without affecting the stabilityof the frequency synthesizer.

According to the present invention, a synthesizer based on aphase-locked loop structure, of the type comprising a reference signalgenerator that generates a reference signal that is connected to a firstphase detector that generates a first phase error signal, that in turnis connected to a first low-pass filter that generates a first filteredphase error signal, and that is connected to a voltage-controlledoscillator whose output is frequency-divided n times lower than thefrequency of the signal at the output of the voltage-controlledoscillator, and wherein the divided output signal is connected to thephase detector and wherein the frequency divider provides a secondoutput signal shifted 90° with respect to its other output signal, whichis provided to a second phase detector that also receives as an inputthe reference signal, and that provides a second phase error signalwhich is in quadrature with the first phase error signal generated bythe first phase detector; a second low-pass filter is connected to thesecond phase detector and provides a second filtered phase error signal;a quadratic correlator receives, as inputs, both of the filtered phaseerror signals and provides a third output signal to the VCO whoseamplitude is proportional to the difference of frequencies between thereference signal and any of the output signals from the frequencydivider.

The quadratic correlator can be either of the balanced type or of theunbalanced type.

With the application of this type of structure, important advantages areobtained, like a fast response to the channel switching, maintaining ahigh spectral purity of the synthesized signal, and using a lowcomplexity structure. This allows it to be used in communication systemswhere a dynamic channel allocation is employed as, for instance, DECT(Digital European Cordless Telecommunication) system.

Other important advantages are the simplicity of the new elements thatcomprise this structure that do not increase its cost appreciably andalso that the working frequency range depends very little on theswitching time and spectral purity of the output signal. Altogether itallows high performances in a frequency range wider than that of theconventional synthesizers.

These and other objects, features and advantages of the presentinvention will become more apparent in light of the detailed descriptionof a best mode embodiment thereof, as illustrated in the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a general block diagram of the synthesizer according to theinvention;

FIG. 2 shows a more detailed block diagram of block 8 in case that abalanced quadratic correlator is used; and

FIG. 3 shows a more detailed block diagram of block 8 in case that anunbalanced quadratic correlator is used.

BEST MODE FOR CARRYING OUT THE INVENTION

The block diagram of FIG. 1 represents a Phase Lock Loop as disclosed inthe present invention. It comprises a reference signal generator 1 thatgenerates an instantly changing frequency reference signal 9, withstability as required by the system. This reference signal 9 provides toa first phase detector 2 and to a second phase detector 6, to becompared with respective phases of output signals 10 and 11 coming froma frequency divider 5 and whose most representative characteristic isthat both signals 10 and 11 are in quadrature, which means that theirrelative phase is shifted by 90°.

Phase error signals 12 and 13 coming respectively from phase detectors 2and 6 provides, also respectively, to the low pass filters 3 and 7,characterised by their high simplicity and whose task is to eliminatethe frequency sum at the output of the phase comparators 2 and 6.

From the above mentioned low pass filters 3 and 7 it is attained firstand second filtered phase error signals 14 and 15, which are shiftedninety degrees with respect to each other and which are provided to aquadratic correlator 8; this last generating a control voltage 16 whoseamplitude is proportional to the difference of frequencies between thereference signal 9 and any of the output signals 10, 11 from thefrequency divider 5.

This control voltage 16 is applied to a VCO 4 (Voltage ControlledOscillator), the frequency of its output signal 17 being the synthesizedfrequency, and that depends for its frequency proportionally on thevoltage applied to its input.

The output signal 17 from the VCO 4 is applied to the frequency divider5, this last attaining two output signals 10 and 11 whose frequency isthe frequency of the output signal 17 from the VCO 4, divided by aN-factor and shifted in phase ninety degrees from each other aspreviously indicated.

FIG. 2 shows a possible implementation of the quadratic correlator 8,which constitutes a balanced quadratic correlator.

It comprises two derivative circuits 18 and 19 which are respectivelysupplied by the filtered phase error signals 14 and 15, generatingrespectively the derivative signals 24 and 25. There is also a firstmultiplier 20 that multiplies the second filtered phase error signal 15by the derivative signal 24 of the filtered phase error signal 14, and asecond multiplier 21 that multiplies the first filtered phase errorsignal 14 by the derivative signal 25 of the second filtered phase errorsignal 15.

The respective output signals 26 and 27 from both multipliers 20 and 21are subtracted, the second from the first, in a subtractor 22, thatattains an output signal 28 whose amplitude has the form K (f₁ -f₂), Kbeing a proportionality constant and f₁ and f₂ respectively thefrequencies of the reference signal 9 and of any of the output signals10, 11 from the frequency divider 5.

This output signal 28 coming from the subtractor 22 is applied to afirst integrator filter 23 that attains the control voltage 16 to beapplied to the VCO 4.

FIG. 3 shows another possible implementation of the quadratic correlator8, which constitutes an unbalanced quadratic correlator which has greatsimplicity.

It comprises a third derivative circuit 29 that attains a derivativesignal 32 of the first filtered phase error signal 14.

This derivative signal 32, coming from the third derivative circuit 29,is provided to a third multiplier 30 that also receives the secondfiltered phase error signal 15 and that generates an output signal 33whose amplitude has the form K (f₁ -f₂) [1+cos 2(ω₁ -ω₂)t] that isproportional, as in the first case, to the frequency difference betweenthe reference signal 9 and any of the output signals 10, 11 of thefrequency divider 5, plus a ripple of frequency twice said frequencydifference, and which is eliminated by an integrator filter 31 thatreceives the output signal 33 of the third multiplier 30 and thatgenerates the voltage control 16 that will be provided to the VCO 4.

We claim:
 1. A frequency synthesizer having a phase lock loop structurefor synthesizing from a reference signal that changes frequencyinstantly, a channel frequency signal for use in transmitting digitalinformation, comprising:a first phase detector (2), responsive to saidreference signal (9), for providing a first phase error signal (12),that in turn is provided to a first low pass filter (3) that provides afirst filtered phase error signal (14); a voltage-controlled oscillator(4), responsive to a third output signal (16), for providing anoscillator output signal (17) provided to a frequency divider (5) thatprovides a first output signal (10) whose frequency is N times lowerthan a frequency of the oscillator output signal (17), and that isprovided to the first phase detector (2) and wherein the frequencydivider (5) provides a second output signal (11) which is shifted ninetydegrees with respect to the first output signal (10); a second phasedetector (6) that is responsive to the reference signal (9) and to thesecond output signal (11), for providing a second phase error signal(13) which is in quadrature with the first phase error signal (12); asecond low pass filter (7) responsive to the second phase error signalfor providing a second filtered phase error signal (15); and a quadraticcorrelator (8) responsive to both the first and second filtered phaseerror signals (14, 15) for providing the third output signal (16) to thevoltage-controlled oscillator (4), the third output signal having anamplitude instantly proportional to a frequency difference between thereference signal (9) and either of the first and second output signals(10, 11).
 2. A frequency synthesizer according to claim 1, wherein thequadratic correlator (8) comprises:a first derivator (18) responsive tothe first filtered phase error signal (14), for providing a firstderived signal (24); a second derivator (19) responsive to the secondfiltered phase error signal (15), for providing a second derived signal(25); a first multiplier (20), responsive to the first derived signal(24) and to the second filtered phase error signal (15), for providing afourth output signal (26); a second multiplier (21), responsive to thesecond derived signal (25) and to the first filtered phase error signal(14), for providing a fifth output signal (27); a first subtractor (22),responsive to the fourth and fifth output signals (26, 27), forproviding a sixth output signal (28) having an amplitude proportional toa difference of frequencies between the reference signal (9) and any ofthe first and second output signals (10, 11); and a first integratorfilter (23), responsive to the sixth output signal (28), for providingthe third output signal (16).
 3. A frequency synthesizer according toclaim 1, wherein the quadratic correlator (8) comprises:a derivator(29), responsive to the first filtered phase error signal (14), forproviding a derived signal (32); a multiplier (30), responsive to thederived signal (32) and the second filtered phase error signal (15), forproviding a multiplier output signal (33) having an amplitudeproportional to a frequency difference between the reference signal (9)and any of the first and second output signals (10, 11) from thefrequency divider (5) plus a ripple of frequency twice said frequencydifference; and an integrator filter (31), responsive to the multiplieroutput signal (33), for providing the third output signal (16).